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| (R) Using the ISL97702 OLED Driver Demo Board Technical Brief June 12, 2006 TB455.0 Introduction The complete schematic of the ISL97702 OLED driver Demo Board is shown in Figure 1. In order to use the demo board properly, it is necessary to understand the purpose and function of the on board jumpers (JP1, JP2, JP3). In the demo board, jumper JP1 is used to enable ISL97702 through the NEN pin. The part is enabled when the NEN pin is connected to GND through JP1. JP2 is used for the selection of the output voltage feedback network. The pre-installed values of resistors R1, R5 and R6 in the demo board schematic set the selectable output voltages to 18.3V and 12.6V. Either of these two output voltages can be selected by shunting JP2 to either VDD or GND. JP3 is used to select either the internal ISL97702 switching frequency, or to synchronize to an external frequency. When JP3 is shunted to VDD, the ISL97702 boost converter switching frequency is internally set to around 1MHz. When JP3 is opened, the NSYNC pin of ISL97702 will connect through the J4 pin of the demo board. To test the demo board, the following procedure must be followed: Shunt JP1 to GND. To enable ISL97702 boost converter. Connect the load. The load is connected through VOUT and GND_OUT terminals. Apply a DC power voltage source. The DC power voltage source is applied through both VDD_IN and GND_IN terminals. For ISL97702, the allowed input voltage range is from 2.3 to 5.5V. Due to the boost function, the input DC voltage must be lower than the output voltage in order to regulate the output voltage. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. J7 C3 OPEN R2 OPEN J2 GND_IN 1 2 J1 VDD_IN VDD C1 100n VDD C9 4.7/10V 3 4 5 J4 NSYNC 3 JP3 U1 GND VDDOUT VDD NSYNC FBO L1 10H VOUT C8 100n C7 3.3F/50V C6 3.3F/50V NEN SEL FB1 8 JPP2 7 VDD 6 1 3 1 2 R1 390k J3 R6 39k LX VOUT 10 9 C4 OPEN C5 OPEN VDD J6 NEN R4 OPEN R5 26.1k R3 OPEN GND_OUT Technical Brief 455 ISL97702 C2 10 JPP2 J5 SEL FIGURE 1. COMPLETED SCHEMATIC OF ISL97702 OLED DEMO BOARD TB455.0 June 12, 2006 Technical Brief 455 ISL97702 Bill of Materials DESIGNATOR C6 C7 C9 C2 L1 R5 R6 C8 C1 R1 J2 J3 JP1 JP2 JP3 J6 J4 R2 C3 J5 J1 J7 R4 R3 PART TYPE 3.3F/50V 3.3F/50V 4.7/10V 47/10V 10H 26.1k 39k 100n 100n 390k GND_IN GND_OUT JUMPER-3PIN JUMPER-3PIN JUMPER NEN NSYNC OPEN OPEN SEL VDD_IN VOUT OPEN OPEN FOOTPRINT 1210 1210 805 1206 6028 603 603 603 603 603 POWERPOST POWERPOST JUMPER-3PIN JUMPER-3PIN JUMPER-2PIN POWERPOST POWERPOST 603 603 POWERPOST POWERPOST POWERPOST 603 603 SUMIDA MANUFACTURER 3 TB455.0 June 12, 2006 Technical Brief 455 Demo Board Layout FIGURE 2. TOP SILKSCREEN OF ISL97702 BOOST DEMO BOARD FIGURE 3. TOP LAYER OF ISL97702 BOOST DEMO BOARD 4 TB455.0 June 12, 2006 Technical Brief 455 Demo Board Layout (Continued) FIGURE 4. BOTTOM LAYER OF ISL97702 BOOST DEMO BOARD Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 5 TB455.0 June 12, 2006 |
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